These inventions relates to a semiconductor memory cell, array, architecture and device, and techniques for reading, controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.
One type of dynamic random access memory cell is based on, among other things, a floating body effect of semiconductor on insulator (“SOI”) transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge in the body region of the transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12, each consisting of transistor 14 having gate 16, an electrically floating body region 18, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
Notably, for at least the purposes of this discussion, logic high or State “1” corresponds to an increased concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or State “1”.